1. Field of the Invention
The present invention relates to an electrically rewritable non-volatile semiconductor storage device and a method of manufacturing the same.
2. Description of the Related Art
Conventionally, LSIs are formed by integration of devices in a two-dimensional plane on the silicon substrate. Although some measures have been taken to reduce the dimension for each device (refinement) to increase memory storage capacity, recent years are facing challenges in such refinement from the viewpoint of cost and technology. Such refinement requires further improvements in photolithography technology. However, in currently available ArF immersion lithography technology, for example, the resolution limit has been reached around the 40 nm design rule and so EUV exposure devices have to be introduced for further refinement. However, the EUV exposure devices are expensive and infeasible in view of the costs. In addition, if such refinement is accomplished, it is assumed that physical improvement limit, such as in breakdown voltage between devices, would be reached unless driving voltage can be scaled. Thus, it is likely that difficulties would be encountered in device operation itself.
Therefore, a large number of semiconductor storage devices have been proposed recently where memory cells are arranged in a three-dimensional manner to achieve improved integration of memory devices (see, Japanese Patent Laid-Open No. 2007-266143).
One of the conventional semiconductor storage devices where memory cells are arranged in a three-dimensional manner uses transistors with cylinder-type structure (Patent Document 1). Those semiconductor storage devices using transistors with cylinder-type structure are provided with multiple laminated conductive layers, corresponding to gate electrodes, and pillar-like columnar semiconductors. Each of the columnar semiconductors serves as a channel (body) part of each of the transistors. Charge accumulation layers that can accumulate charges are provided around the columnar semiconductors. Such configuration including laminated conductive layers, columnar semiconductors, and memory gate insulation layers is referred to as a “memory string”.
In the semiconductor storage device with the memory strings, reliability of the memory gate insulation layers of, and data retaining characteristics of the semiconductor storage device are determined by a structure and a manufacturing method of the charge accumulation layers.
For example, conventional methods of manufacturing memory strings are generally explained as follows. Firstly, a hole is formed to penetrate laminated conductive layers and interlayer insulation layers that are alternately laminated on the silicon (Si) substrate. Then, a block insulation layer and a charge accumulation layer (SiN) are formed on the respective side surfaces, facing the hole, of the laminated conductive layers and the interlayer insulation layers. Thereafter, any material, such as silicon nitride (SiN) or silicon oxide (SiO2), is removed from the bottom portion of the hole by Reactive Ion Etching (RIE) for establishing a contact with the conductive layer or the silicon (Si) substrate that is provided below the hole. At this moment, in addition to the bottom portion of the hole, the block insulation layer (gate insulation layer) facing the laminated conductive layers could also be damaged by RIE, which would be a major cause of gate leakage. Therefore, with the conventional manufacturing methods as mentioned above, erroneous write operations to irrelevant cells could occur.
In addition, for example, with the conventional structure, a charge accumulation layer is formed over the multiple laminated conductive layers. Therefore, charges can diffuse in the charge accumulation layer, which may result in degradation of data retaining characteristics.